1. Field of the Invention
The present invention relates generally to semiconductor devices formed of a plurality of semiconductor components arranged on a common substrate, and more particularly, to a method of and circuitry for reducing variations in operating characteristics of such devices that tend to occur as a result of substrate resistance between the components. The invention has particular application to an array of nonvolatile semiconductor memory devices formed of floating gate type field effect transistors wherein source resistance formed by substrate regions between transistors tends to vary the apparent threshold voltages thereof and, accordingly, reduces the reliability of information read out from the array.
2. Description of the Prior Art
A memory device for storing information in a nonvolatile manner has been well known in the art. As a memory element in such a nonvolatile semiconductor memory device, a field effect transistor comprising a floating gate for holding charges corresponding to information is generally employed.
FIG. 1 is a diagram showing schematic structure of the whole of a conventional nonvolatile semiconductor memory device. In FIG. 1, the conventional nonvolatile semiconductor memory device comprises a memory cell array 1 having memory cells arranged in a plurality of rows and columns for storing information in a nonvolatile manner, an address buffer 2 receiving an address signal externally applied for generating an internal address signal, an X decoder 3 for decoding an internal row address signal from the address buffer 2 for generating a signal for selecting a corresponding row from the memory cell array 1, a Y decoder receiving an internal column address signal from the address buffer 2 for generating a signal for selecting a corresponding column from the memory cell array 1, a Y gate 5 responsive to a column decode address signal from the Y decoder 4 for selectively connecting the selected column in the memory cell array 1 to an input/output portion, a (sense amplifier+input/output buffer+write-in circuit) 6 connected to the selected column for writing/reading out information to or from the selected memory cell through the Y gate 5, a control signal generating circuit 7 for generating a signal (a chip enable signal CE, an output enable signal OE or the like) for controlling an operation mode of the memory device, a Vpp/Vcc switching circuit 8 responsive to an operation mode designating signal from the control signal generating circuit 7 for generating either of a high voltage Vpp or a power-supply voltage Vcc and applying the same to the X decoder 3, and a Vpp'/Vcc switching circuit 9 responsive to the operation mode designating signal from the control signal generating circuit 7 for generating either one of a second high voltage Vpp' or the power-supply voltage Vcc and applying the same to the Y decoder 4.
A voltage from the Vpp/Vcc switching circuit 8 is supplied to the selected row through the X decoder 3. On the other hand, the high voltage Vpp' or the power-supply voltage Vcc generated in the Vpp'/Vcc switching circuit 9 is applied to the Y gate 5 through the Y decoder 4. The (sense amplifier+write-in circuit+input/output buffer) 6 is responsive to the operation mode designating signal from the control signal generating circuit 7 for applying the write high voltage Vpp' to the selected column through the Y gate 5 in a write mode while receiving information in the selected column through the Y gate 5 for outputting data D amplified by a sense amplifier in a read mode. More specifically, a write-in circuit is activated in the write mode and a sense amplifier is activated in the read mode.
FIG. 2 is a diagram showing specific structure of a memory cell array portion and a Y gate portion shown in FIG. 1. In FIG. 2, the memory cell array 1 has memory transistors MTr.sub.11 to MTr.sub.1n, . . . , MTr.sub.m1 to MTr.sub.mn arranged in rows and columns and each comprising a field effect transistor having a floating gate for storing information in a nonvolatile manner. Respective control gate selecting signals G1 to Gm from the X decoder 3 are applied to control gates of the memory transistors in corresponding row. More specifically, a word line WL1 is connected to the control gates of the memory transistors MTr.sub.11 to MTr.sub.1n in the first row, so that the control gate selecting signal G1 from the X decoder 3 is transmitted onto these control gates through the word line WL1. A word line WL2 is connected to the control gates of the memory transistors MTr.sub.21 to MTr.sub.2n in the second row, the control gate selecting signal G2 from the X decoder 3 is transmitted onto the control gates through the word line WL2. In the same manner, a word line WLm is connected to the control gates of the memory transistors MTr.sub.m1 to MTr.sub.mn in the m-th row, so that the control gate selecting signal Gm from the X decoder 3 is transmitted onto the control gates through the word line WLm.
The memory transistors in one column have their drains connected to single drain line. More specifically, the drains of the memory transistors MTr.sub.11 to MTr.sub.m1 in the first column are connected commonly to a drain line D1. The drains of the memory transistors MTr.sub.12 to MTr.sub.m2 in the second column are connected commonly to a drain line D2. In the same manner, the drains of the memory transistors MTr.sub.1n to MTr.sub.mn in the n-th column are connected commonly to a drain line Dn. In order to connect a source of each memory transistor to a ground, source lines S1 and S2 coupled to the ground potential are provided in parallel to the drain lines D1 to Dn every plurality of memory transistors (n memory transistors in FIG. 2).
The drain lines D1 to Dn are connected to Y gate transistors Tr.sub.1 to Tr.sub.n included in the Y gate 5, respectively. The Y gate transistors Tr.sub.1 to Tr.sub.n have their gates coupled to Y gate selecting signals Y1 to Yn from the Y decoder 4, respectively. Consequently, a single Y gate transistor is rendered conductive in response to the Y gate selecting signal from the Y decoder 4, so that a single drain line is connected to the (sense amplifier+I/O buffer+write-in circuit) 6 through the Y gate 5. In general, a memory transistor comprises a field effect transistor having source and drain diffusion regions. Resistance represented by R in FIG. 2 shows resistance of the source diffusion region. The source diffusion region will be described below.
FIGS. 3A and 3B are diagrams showing a memory transistor, where FIG. 3A shows the plane layout thereof and FIG. 3B shows a cross-sectional structure taken along a line A--A in FIG. 3A.
In FIG. 3A, source lines S1 and S2 are provided in parallel with drain lines D1 to Dn. A word line WL is provided perpendicularly intersecting with the source lines S1 and S2 and the drain lines D1 to Dn. Each of the source lines S1 and S2 are connected to a source diffusion region 20 through a contact hole 21. The source diffusion region 20 is provided in common for memory transistors in one row. In addition, each of the drain lines D1 to Dn is connected to a drain diffusion regions 25 through a contact hole 26. The word line WL also serves as a control gate CG of a memory cell. A floating gate FG is formed over a channel region of the memory transistor under the word line WL.
In FIG. 3B, a single memory transistor generally comprises an N.sup.+ type impurity region 20 serving as a source and an N.sup.+ type impurity region 25 serving as a drain each formed in a predetermined region on, for example, a p type semiconductor substrate 100. The N.sup.+ impurity region 25 for a drain is provided in common for two memory transistors. The N.sup.+ type impurity region 25 for a drain is connected to a drain line D formed of, for example, aluminum. A floating gate FG for storing charges and a control gate CG receiving a signal for controlling injection of charges to the floating gate as well as for a read operation are provided over a channel region between the N.sup.+ type impurity regions 20 and 25. In this kind of electrically programmable read-only memory (referred to as EPROM hereinafter), a high voltage Vpp and a second high voltage Vpp' (Vpp&gt;Vpp') are generally applied to the control gate CG and the drain impurity region 25, respectively, in a write operation, and the source impurity region 20 is coupled to a ground potential. Consequently, hot electrons are produced by a high electric field in the vicinity of the drain region 25 and avalanche-injected into the floating gate FG. This state is generally referred to as a write state in the EPROM. Thus, when electrons are injected into the floating gate FG, the threshold voltage of the memory transistor is shifted higher, so that the memory transistor is not easily rendered conductive.
Furthermore, since the source region comprises an impurity region, the source region has an inherent resistance value R. Referring now to FIGS. 1 to 3B, description is made on operation in the conventional nonvolatile semiconductor memory device.
A data writing operation is now described. The nonvolatile semiconductor memory device is set to the write mode by the signal from the control signal generating circuit 7, so that the Vpp/Vcc switching circuit 8 and the Vpp'/Vcc switching circuit 9 generate the high voltages Vpp and Vpp', respectively. At the same time, in the (sense amplifier+input/output buffer+write-in circuit) 6, an input buffer and a write-in circuit included therein are connected to the Y gate 5 responsive to the write mode designating signal from the control signal generating circuit 7. Data to be written is applied to the input buffer. When the external address is accepted and the internal row address and the internal column address are produced by the address buffer 2, the X decoder 3 and the Y decoder 4 decode the address received from the address buffer 2 to select corresponding row and column. The X decoder 3 transmits a signal of high voltage Vpp level to a selected word line as a control gate selecting signal. Consequently, the high voltage Vpp is applied to each control gate CG of the memory transistor connected to a selected row. On the other hand, a Y gate selecting signal of the high voltage Vpp' is transmitted to the Y gate transistor corresponding to a column selected by the Y decoder 4. On this occasion, the write high voltage Vpp' is supplied from the write-in circuit included in the (sense amplifier+input/output buffer+write-in circuit) 6 (all memory transistors are now in an erased state), and is transmitted to the drain line through the Y gate transistor which is rendered conductive in the Y gate 5. As a matter of convenience in discussion, it is assumed that the state in which charges are injected into the floating gate FG of the memory transistor is referred to as a state of logic "0" and the state in which charges are not injected into the floating gate FG corresponds to a state of logic "1". When data to be written is "0", the high voltage Vpp' (about 10.5 V) is applied from the write circuit. Consequently, in the memory transistor having a drain line receiving the write high voltage Vpp', hot electrons are produced and accelerated along an electric field which is formed between the drain region and the control gate by the high voltage Vpp applied to the control gate, to be avalanche-injected into the floating gate FG. Thus, the threshold value of a memory transistor having information of logic "0" is shifted higher, resulting in the state in which logic "0" is written. In the write operation, since a Y gate transistor connected to a non-selected drain line remains off-state, a conduction path between the non-selected drain line and the source lines S1 and S2 is established by way of the source diffusion regions of the memory transistor connected to the selected word line through on-resistance of the memory transistor, resulting in the state in which the non-selected drain line is connected to the ground (all the memory transistors connected to the selected word line are turned on irrespective of whether or not information is written because the write high voltage Vpp is applied to the control gates thereof). In the above described structure, since all memory cells are in an erase state before writing of data, only a memory cell to which logic "0" is to be written is accessed so that charges are injected into the floating gate thereof.
A read operation is now described. In this case, the read mode designating signal is applied to the Vpp/Vcc switching circuit 8 and the Vpp'/Vcc switching circuit 9 from the control signal generating circuit 7. Consequently, both the Vpp/Vcc switching circuit 8 and the Vpp/Vcc switching circuit 9 generate a signal of potential Vcc and apply the same to the X decoder 3 and the Y decoder 4, respectively. The X decoder 3 is responsive to an applied external address signal to select a single word line to transmit to the selected word line a control gate selecting signal Gi (i: any of 1 to m) of power-supply potential Vcc level. On this occasion, the threshold voltage of a memory transistor storing logic "0", i.e., a transistor having a floating gate with charges injected thereinto generally is at a level of as high as about 6 V. Thus, since the power-supply potential Vcc level is generally about 5 V, the memory transistor storing logic "0" is turned off. On the other hand, since the threshold voltage of a memory transistor storing logic "1" is generally about 1.5 V, the memory transistor is turned on. Then, the Y decoder 4 is responsive to the internal column address signal for outputting a Y gate selecting signal Yi (i: any of 1 to n), and for turning on a corresponding Y gate transistor Tri in the Y gate 5. Consequently, the selected signal drain line Di is connected to a sense amplifier and an output buffer. In the (sense amplifier+input/output buffer+write circuit) 6, the Y gate 5 is connected to a path of the sense amplifier and the output buffer in response to the read mode designating signal from the control signal generating circuit 7. In the read mode, a read potential (generally about 1 V) is generated from the read potential generating circuit included in the (sense amplifier+output buffer) and transmitted to the selected drain line Di through the Y gate transistor in the on state included in which is turned on, the Y gate 5. Consequently, when a memory transistor located at an intersection of a selected control gate line (i.e., word line) and a selected drain line has information of logic "0", the memory transistor is turned off. On the other hand, when a selected memory transistor has information of logic "1", the memory transistor is turned on, so that current flows through the memory transistor in an on state. It is determined by the sense amplifier whether or not current flows through the selected drain line. The result is transmitted to the output buffer, so that data is read out. In the read mode, a voltage applied to the control gate is lower than the power-supply potential Vcc and the potential Vpp applied in the write mode. Thus, when a non-selected memory transistor connected to the same word line as that the selected memory transistor is connected to stores logic "1", the memory transistor is turned on, so that non-selected drain line is connected to the source metal interconnections S1 and S2 through the memory transistor in the on state. When the non-selected memory transistor stores information "0", the memory transistor remains turned-off, so that the drain line is rendered electrically floating.
As described in the foregoing, in the conventional nonvolatile semiconductor memory device, at the time of writing data, since the Y gate transistors connected to the non-selected drain lines remain turned off, the non-selected drain lines are connected to the source diffusion regions of the respective memory transistors in the on state through the on-resistances of the memory transistors connected to the same word line as that the selected memory transistor is connected to, and are connected to the source metal interconnections (source lines) S1 and S2 to be connected to the ground. Similarly, in the read mode, since the voltage applied to the gates of the memory transistors is smaller than that applied in the write mode, a memory transistor connected to the same word line as that which the selected memory transistor is connected to is turned on if the memory transistor stores logic "1". Thus, the non-selected drain lines are connected to the source lines S1 and S2 through the on resistance of the corresponding memory transistor in the on state and connected to the ground. On the other hand, if a memory transistor connected to the same word line as that the selected memory transistor is connected to stores logic "0", the memory transistor remains turned-off because the threshold voltage thereof is as high as about 6 V, so that the drain lines connected to the off state memory transistors are rendered electrically floating. As described above, if the memory transistors store logic "0", the threshold voltages thereof are generally about 6 V. If the memory transistors store logic "1", the threshold voltages thereof are generally about 1.5 V.
Now the source potentials of the memory transistor are discussed. The source region of each of the memory transistors is generally grounded by the source metal interconnections S1 and S2. However, in practice, there exists an N.sup.+ type impurity diffused region with a resistance before a source region reaches the source interconnections S1 and S2. Referring to the drawings, this state will be described.
FIG. 4 is a diagram showing source resistance which memory transistors MTr.sub.11 and MTr.sub.12 form between source lines S1 and S2, and current flowing through the memory transistors at the time of writing and reading out data.
FIG. 5 is a diagram showing source resistance of each memory transistor in the case in which source lines are provided every eight memory transistors. More specifically, as shown in FIG. 5, if source contacts are provided every eight memory transistors so that source diffusion regions are connected to source lines, combined resistance of the n-th source region counted from a source metal interconnection S1 to the source metal interconnections S1 and S2 is given by the following equation: EQU Rn=R.n(9-n)/9(n=1.about.8)
Thus, from this equation, it can be seen that source resistance of a memory transistor which is the closest to the source line is 0.89R (=R.8/9) and a resistance value formed between the source region of a memory transistor and the source metal interconnections becomes larger in order as the memory transistor approaches the central portion.
When access to the memory transistor MTr.sub.11 is made to write or read out information, the source potential is higher, by R1.I, than a ground potential. Then, when access to the memory transistor MTr.sub.12 is made to write or read out information, the source potential is higher, by R2.I, than the ground potential. A memory transistor generally starts to be conductive when a voltage higher, by a threshold voltage, than the source potential thereof is applied to the gate electrode. Thus, when the source potential becomes higher, the gate potential of the memory transistor becomes virtually lower. Thus, the threshold voltage thereof becomes virtually higher. Consequently, if potentials applied respectively to a gate and a drain of a memory transistor are all the same for all memory transistors, access for reading out and writing information becomes more difficult in the memory transistor having higher source potential. More specifically, in FIG. 4, for example, since the source potential of the memory transistor MTr.sub.12 is higher than that of the memory transistor MTr.sub.11, the threshold voltage of the memory transistor MTr.sub.12 becomes virtually higher, so that information of the memory transistor MTr.sub.12 can not be correctly read out or written. More specifically, if the same gate potential is applied for the memory transistors, a desired amount of charges can not be injected into the floating gate of the memory transistor MTr.sub.12, so that a desired shift value can not be applied to the threshold voltage thereof. In addition, at the time of reading out data, a case where a memory transistor to be turned on or a memory transistor storing logic "1", is not turned on. Furthermore, even if the memory transistor storing logic "1" is turned on, the on state of the transistor becomes incomplete or shallow one. Consequently, a desired amount of current can not be caused to flow through the drain line, so that data can not be correctly read out or written.
Additionally, referring to a plurality of memory transistors formed between the two source metal interconnections S1 and S2, a memory transistor remotely provided from the source metal interconnection (source line), i.e., a memory transistor provided in the central portion in a single memory transistor block, the threshold voltage thereof becomes virtually higher, so that it becomes difficult to correctly read out or write data thereof.
More specifically, in such a conventional nonvolatile semiconductor memory device, when data is read out or written, in a memory transistor remotely provided from the source metal interconnection (or source line), the source potential thereof becomes higher than the ground potential depending on the distance to the source line. Thus, the threshold voltage of the memory transistor becomes virtually higher with the distance to the source line longer. Even if the same gate potential is applied, the apparent gate potential changes depending on the position in which the memory transistor is provided. Consequently, at the time of writing data, a desired amount of shift in threshold voltage can not be provided. In addition, a memory transistor to be turned on (i.e., a memory transistor storing information "1") can not be turned on as desired at the time of reading out data. Therefore, desired read current can not be provided to the drain line, so that it becomes difficult to surely write or read out information.
Additionally, if the number of source metal interconnections is increased in order to solve the above described problem, reduced source resistance of each memory transistor can be obtained. However, in that case, the area required for source metal interconnection is increased due to additional source metal interconnections, so that it becomes difficult to increase integration density of a memory cell array.
Fundamental structure such as structure of a memory cell, a memory cell array and a decoder in the conventional EPROM is reviewed in a technical article entitled "E-PROMs graduate to 256-K density with scaled n-channel process", Electronics 1, Feb. 24, 1983, pp. 4-113-4-117 published by Intel Corporation. However, this article does not consider a variation of a source potential caused by the difference in source resistance among the memory transistors.